Modern day semiconductor electronic devices include power transistor devices and integrated circuit devices comprising many transistors formed on a small section of semiconductor material. It is common for thousands of such devices to be simultaneously formed on a single wafer of crystalline semiconductor material. Advances in semiconductor processing have enabled volume manufacture of such electronic devices having feature sizes less than 0.25 micron, and there is progress toward geometries below 0.10 micron.
All transistors operate based on the presence of impurities, commonly referred to as dopants, placed in the lattice structure of the semiconductor material. By varying the concentration of dopants in select regions of the semiconductor crystal lattice one can alter the conductivity and other electrical characteristics of the transistor. For example, the voltage at which a transistor begins to switch into a conducting state, as well as the on-off switching speed of the transistor, may depend in part on the presence of predefined dopant concentration profiles in critical regions of the semiconductor material.
For conventional silicon transistors having sub-micron feature sizes these requirements are typically met through multiple high energy implantations of various dopant ions into the surface of the semiconductor wafer, followed by temperature cycling of the wafer. That is, multiple heat treatments are relied upon to thermally diffuse the implanted dopants until desired dopant profiles are attained in or near the transistor regions of the semiconductor material.
Such diffusions are commonly achieved by thermal annealing of the semiconductor wafer. While it is typically a goal of dopant diffusion to drive the dopant deeper into the semiconductor material (relative to the surface), and there is little ability to control the direction of diffusion, the dopant moves in a lateral direction (along the surface) as well. Conventionally, the distances dopants travel from an implant region are controlled by the time and temperature profile of the thermal diffusion cycle.
By controlling the energy and dose of the ion implant as well as the profile of the thermal diffusion cycle, a desired depth of diffusion can be attained without exceeding the maximum tolerable lateral diffusion. Nonetheless, the inherent features of thermal diffusion impose limitations on spacings between device features, e.g., the source, gate and drain regions of a lateral metal oxide silicon field effect transistor (MOSFET). This is particularly true as lateral device geometries progress below 0.2 micron.
The lateral geometry constraints due to diffusion have been addressed by designing shallow junction depths and by performing relatively brief thermal treatments commonly referred to as the rapid thermal anneal (RTA) or rapid thermal diffusion (RTD) in which the temperature of a wafer is rapidly cycled to a peak value, held at the maximum temperature for a short period and then quickly cooled.
An additional challenge relative to reduced geometries is the greater sensitivity to high temperature processing of certain materials preferred for manufacturing high speed circuitry with smaller than 0.20 micron feature sizes. These materials include conductors and dielectrics which help sustain or improve the speed and integrity of transistor devices as device layers become thinner and lateral geometries continue to shrink. Generally, as devices shrink the thermal budget becomes more restricted.
Further, the entire manufacturing process must be designed to account for the effect each temperature cycle has on the materials subjected to the heat treatment. In many instances the sequence of manufacturing steps is constrained to avoid subjecting certain materials to undesirable temperatures. At times this leads to complex and costly process steps. For example, it has been proposed that the high temperature anneal of source/drain regions in a MOSFET (which effect dopant diffusion) precede (rather than follow) the formation of the gate dielectric. While this would enable incorporation of a temperature-sensitive but preferred dielectric material, it renders alignment of the source/drain regions about the gate structure a more complex process.